1. Field of the Invention
This invention relates generally to the processing of signals in communication systems and, more particularly, to the processing of signals by adaptive or equalizer filter circuits. Equalizer filter circuits or adaptive filter circuits are used to compensate for distortion introduced into the channel during the transmission of signals. The present invention has particular applicability to modem units.
2. Description of the Prior Art
Referring to FIG. 1, a block diagram of a transceiver unit capable of advantageously using the present invention is shown. INPUT SIGNALS are applied to symbol decoder and side-stream descrambler unit 11. Output signals from the symbol encoder and side-stream scrambler unit 11 are applied to transmitter unit A 15 and to transmitter unit B 13. The output signals from transmitter unit A 15 are applied to hybrid unit 18, while the output signals from transmitter unit B 13 are applied to hybrid unit 17. The output signals from hybrid unit 17 and hybrid unit 18 are applied to cable 19. Signals from cable 19 are transmitted through hybrid unit 17 to receiver unit B 14 and through hybrid unit 18 to receiver unit A 16. The output signals from receiver unit A 16 and from receiver unit B 14 are applied symbol decoder and side-stream descrambler unit 12. The output signals from the symbol decoder and side-stream descrambler unit 12 are the OUTPUT SIGNALS from the transceiver.
In the transmitter unit A 15, the input signals are applied to a digital transmit filter unit 151. The output signals from the digital transmit filter unit 151 are processed by an digital-to-analog converter unit 152 and applied to an analog transmit filter unit 153. The output signal of the analog transmit unit 153 is the output signal of the transmitter A 15 which is applied to a hybrid unit 18. The transmitter B 13 is implemented in a similar manner.
With respect to the receiver A 16, the output signals from the hybrid unit 18 are applied to a VGA unit 169. The output signals from the VGA unit 169 are processed by an analog receive filter unit 168 and applied to an analog-to-digital converter unit 167. Output signals from the analog-to-digital converter unit 167 are applied to a digital linear forward equalizer unit 166 and to a gain, timing, control unit 170. The signals from the digital linear forward equalizer unit 166 are applied to a summation network 165 and to the gain, timing and control unit 170. The gain, timing and control unit 170 applies control signals to the VGA unit 169 and to the analog-to-digital converter unit 167. The summation unit 165 also receives signals from an echo canceller unit 161, from a NEXT canceller unit 162 and from a feedback filter/noise predictor unit 164. Output signals from the summation unit 165 are applied to a decision unit 163. The decision unit 163 provides the output signal for receiver A 16. The output signal from the decision unit 163 is also applied to the feedback filter/noise prediction unit 164. The decision unit 163 applies an error signal to the echo canceller unit 161, to NEXT canceller unit 162, to feedback filter/noise reduction unit 164, and to digital linear forward equalizer unit 166. The echo canceller unit also receives signals which are applied to the transmitter A 15 associated with the receiver A 16, while the NEXT canceller unit 162 receives an input signal from the transmitter B 13 not associated with the receiver unit A 16 which includes the NEXT canceller unit 162. The receiver B 13 is implemented in a manner similar to receiver A 16.
Referring to FIG. 2, a block diagram of an adaptive equalizer filter unit 20, such as would be used to implement the echo canceller unit 161 and the NEXT canceller unit 162 of FIG. 1, is shown. The equalizer unit 20 includes a multiplicity N of stages. Each stage n of the equalizer unit 13 includes a delay line D.sub.n, (the delay line D.sub.0 is shown with dotted lines because the presence of this delay line is not needed to the operation of filter 20. The delay lines D.sub.0 -D.sub.N-1 of all of the stages are coupled in series. The output terminal of each delay line D.sub.n is coupled, in addition to being coupled to the next sequential delay line D.sub.n+1, to a multiplier unit M.sub.n associated with the n.sup.th stage and to an input terminal of update unit U.sub.n associated with the n.sup.th stage. Each multiplier unit M.sub.n also receives a coefficient signal C.sub.n. The coefficient signal C.sub.n is a signal group stored in the update unit U.sub.n which is updated U.sub.n in response to an ERROR signal e and the output signal of delay line D.sub.n. An ERROR signal e is generated as a result of each signal group processed in the decision unit shown in FIG. 1. The product of the signals C.sub.n and the output signal from delay line D.sub.n formed in multiplier unit M.sub.n is applied to one terminal of adder unit A.sub.m. The adder unit A.sub.m also receives an output signal from one of the neighboring filter stages. The adder units A.sub.0 -A.sub.M-1 are the first stage of an adder tree, the remaining adder units would be included in element 29. The output signals of the adder tree, including the adder units A.sub.0 -A.sub.M-1 and the element 29, are the DATA OUT signals (X').
The signals applied to the multiplier unit M.sub.n are the following:
X.sub.n is the output signal from delay line D.sub.n, and PA1 W.sub.n is given by the formula W.sub.n,t =W.sub.n,t-1 +.mu..star-solid.e.sub.t.star-solid.X.sub.n,t, where .mu. is a constant.
The output signal of the multiplier unit is given by I.sub.n,t =W.sub.n,t.star-solid.X.sub.n,t.
As a result of these equations, three multiplication operations are required are required for each stage of the equalizer filter. However, the selection of the constant .mu. has a flexibility which permits the execution of the multiplication operation by means of a shift operation, an operation which is not apparatus intensive. The two remaining multiplication operations, when implemented with typical multiplier apparatus, can require extensive space on the integrated circuit board.
Referring to FIG. 3, a schematic block diagram of an update unit 30 (U.sub.n) is shown. The update unit 30 has a multiplier unit 31 which receives the filter constant .mu., the error signal e.sub.t, and the data signal X.sub.n,t. The product formed by these three quantities are applied to an input terminal of adder unit 33. Also applied to an input terminal of adder unit 33 is the previously formed coefficient W.sub.n,t-1 stored in register 32. The output signal of adder unit 33 is the coefficient W.sub.n,t. The coefficient W.sub.n,t is applied to multiplier unit M.sub.n associated with same stage of the adaptive filter unit as the update unit U.sub.n and the coefficient W.sub.n,t is applied to register 32 to be used in generating the next coefficient W.sub.n,t+1.
As will be clear, the multiplication of the error signal e and the data signal X.sub.n will require complex apparatus. In addition, each stage of the adaptive equalizer filter unit requires a multiplier unit. Therefore, a substantial portion of the components implementing the adaptive equalizer filters and, consequently, the transceiver itself will be dedicated to implementation of the multiplier units. In the present transceiver, the information is formatted into five signal levels. These signal levels are converted into analog signals and transmitted over a transmission medium (cable). The transceiver receives similarly encoded signals and the original five levels recovered.
A need has therefore been felt for apparatus and for an associated method to reduce the number of components required to perform the multiplication operation of the update unit in an adaptive equalizer unit in the transceiver described above.